1. Field of the Invention
The present invention relates to a memory cell circuit comprising a plurality of memory cells and a layout pattern thereof, and, more particularly, to a memory cell circuit and a layout pattern of a highly integrated memory cell circuit comprising memory cell arrays in which each memory cell has a small aspect ratio.
2. Description of the Prior Art
First conventional example
FIG. 6 is a diagram showing a layout pattern of conventional memory cells to form a memory cell array in a memory cell circuit. For example, the memory cell circuit has a configuration shown in FIG. 1. In FIG. 6, the reference characters n1 to n16 designate first to sixteenth N conductivity type Metal Oxide Semiconductor (NMOS) transistors, respectively. The reference characters p1 to p16 denote first to sixteenth P conductivity type Metal Oxide Semiconductor (PMOS) transistors, respectively. In addition, the reference characters Gn1 to Gn16 indicate gate electrodes of the first to sixteenth NMOS transistors n1 to n16, Sn1 to Sn16 designate source regions of the first to sixteenth NMOS transistors n1 to n16, and Dn1 to Dn16 denote drain regions of the first to sixteenth NMOS transistors n1 to n16, respectively. The reference characters Gp1 to Gp16 designate gate electrodes of the first to sixteenth PMOS transistors p1 to p16. The reference characters Sp2, Sp3, Sp6, Sp8, Sp9, Sp10, Sp11, Sp14, and Sp15 denote source regions of the second, third, sixth, eighth, ninth, tenth, eleventh, fourteenth, and fifteenth PMOS transistors p2, p3, p6, p8, p9, p10, p11, p14, and p15, respectively.
The reference characters Dp2, Dp3, Dp6, Dp8, Dp9, Dp10, Dp11, Dp14, and Dp15 indicate drain regions of the second, third, sixth, eighth, ninth, tenth, eleventh, fourteenth, and fifteenth PMOS transistors p2, p3, p6, p8, p9, p10, p11, p14, and p15, respectively.
The reference character W0BL designates a first write-in bit line made up of a first layer wiring, W0BLC denotes a second write-in bit line made up of the first layer wiring, W0WL0 designates a first write-in word line made up of a second layer wiring, W0WL1 denotes a second write-in word line made up of the second layer wiring, R1WL0 designates a first read-out word line made up of the second layer wiring, R1WL1 denotes a second read-out word line made up of the second layer wiring, and R1BL indicates a read-out bit line made up of the first layer wiring.
The reference character VDD designates a power source line made up of the first layer wiring, and GND indicates a ground line made up of the first layer wiring.
The first layer wiring is formed on the NMOS transistors and the PMOS transistors and the second layer wiring is formed on the first layer wiring.
In FIG. 6, the first layer wirings are shown by using solid lines and the second layer wiring by using hatching lines. In addition, in FIG. 6, open quadrilaterals indicate contact holes through which the first layer wirings are electrically connected to the gate electrodes, the source regions, and the drain regions, and quadrilaterals including a symbol "X" denotes bi-holes through which the first layer wirings and the second layer wirings are connected electrically.
As shown in FIG. 6, in the conventional layout pattern of the memory cell in order to form the memory cell circuit shown in FIG. 1, a row direction is a direction of the transistor array and a direction on which the transistor arrays are adjacent to each other is a column direction. A basic cell comprises a pair of the NMOS transistor and the PMOS transistor. In addition, the two basic cells in row direction and the eight basic cells in column directions are formed, and a plurality of word lines are formed in the row direction and a plurality of bit lines are formed in the column direction.
Second conventional example.
FIG. 7 is a diagram showing a layout pattern of another conventional memory cells to form a memory cell circuit, for example it having the configuration shown in FIG. 4. In FIG. 7, the reference characters n1 to n16 designate first to sixteenth NMOS transistors, respectively. The reference characters p1 to p16 denote first to sixteenth P MOS transistors, respectively. In addition, the reference characters Gn1 to Gn16 indicate gate electrodes of the first to sixteenth NMOS transistors n1 to n16, Sn1 to Sn12 designate source regions of the first to eleventh NMOS transistors n1 to n12, and Dn1 to Dn12 denote drain regions of the first to eleventh NMOS transistors n1 to n12, respectively. The reference characters Gp1 to Gp16 designate gate electrodes of the first to sixteenth PMOS transistors p1 to p16. The reference characters Sp2, Sp3, Sp6, Sp7, Sp8, Sp9, Sp10, and Sp11 denote source regions of the second, third, sixth, seventh, eighth, ninth, tenth, and eleventh PMOS transistors p2, p3, p6, p7, p8, p9, p10, and p11, respectively. The reference characters Dp2, Dp3, Dp6, Dp7, Dp8, Dp9, Dp10, and Dp11 indicate drain regions of the second, third, sixth, seventh, eighth, ninth, tenth, and eleventh PMOS transistors p2, p3, p6, p7, p8, p9, p10, and p11, respectively.
The reference character W0BL designates a first write-in bit line made up of a first layer wiring, W0BLC denotes a second write-in bit line made up of the first layer wiring, W0WL0 designates a first write-in word line made up of a second layer wiring, W0WL1 denotes a second write-in word line made up of the second layer wiring, R1WL0 designates a first read-out word line made up of the second layer wiring, R1WL1 denotes a second read-out word line made up of the second layer wiring, and R1BL indicates a read-out bit line made up of the first layer wiring.
The reference character VDD designates a power source line made up of the first layer wiring, and GND indicates a ground line made up of the first layer wiring. The first layer wiring is formed on the NMOS transistors and the PMOS transistors and the second layer wiring is formed on the first layer wiring.
In FIG. 7, the first layer wiring is shown by using solid lines and the second layer wiring by using hatching lines. In addition, in FIG. 7, open quadrilaterals indicate contact holes through which the first layer wiring is electrically connected to the gate regions (or gate electrodes), the source regions, and the drain regions, and quadrilaterals including a symbol "X" denotes bi-holes through which the first layer wirings and the second layer wirings are connected electrically.
As shown in FIG. 7, in the conventional layout pattern of the memory cell in order to form the memory cell circuit shown in FIG. 4, a row direction is a direction of the transistor array and a direction on which the transistor arrays are adjacent to each other is a column direction. A basic cell comprises a pair of the NMOS transistor and the PMOS transistor. In addition, the two basic cells in row direction and the eight basic cells in column directions are formed, and a plurality of word lines are formed in the row direction and a plurality of bit lines are formed in the column direction.
Because the conventional memory cell layout pattern has the configuration described above shown in FIGS. 6 and 7, there is a drawback that the aspect ratio of each memory cell is large. That is, the aspect ratio of each memory cell is a ratio of a length and a wide of each memory cell, or a ratio of a rectangular length (in row direction) and a lateral length (in column direction) of each memory cell. In the conventional memory cell array in which conventional memory cells are arranged in a array shape, the length in the rectangle direction (along the row direction) depends on the number of bits and the length in the lateral direction (along the column direction) depends on the number of words. Thereby, when the number of bits is greater, the aspect ratio of each memory cell is also greater, so that there is a drawback that it is difficult to form wiring in a semiconductor chip because a shape of a Random Access Memory (RAM) having a large number of bits becomes a depth form when the RAM is fabricated by using a plurality of memory cells having a larger aspect ratio.